1. Field of the Invention
This invention relates to an input buffer architecture. More particularly, it relates to a CMOS input buffer and a method for supporting multiple I/O standards.
2. Description of the Related Art
Field Programmable Gate Arrays (FPGA) are frequently used for various applications and are therefore, interfaced with various devices operating at varied interfacing standards (e.g., LVTTL, LVCMOS, LVCMOS2, LVCMOS1.8, 1.5, 1.2, HSTL, SSTL, GTL, GTL+ etc.). Due to the vast and diverse field of applications of FPGAs, it becomes desirable to have their input circuits capable of receiving signals of different voltage swings in conformance with interfacing standards and convert them into core-acceptable voltage swings.
Existing input circuits for FPGAs use multiple input buffers, each designed to support one or more compatible interface standards. Output of a desired input buffer is selected from a multiplexer and connected to the core. Such an input circuit shown in FIG. 1 includes an input circuit 199, which includes three input receivers 150, 140, 141 and a multiplexer 160. Input receiver 150 is a Schmitt trigger having its input connected to an input pad 180 and having an output 190 connected to one of the inputs of multiplexer 160. The input receiver 150 is structured to accept input voltage swings in general purpose interface environments like LVTTL, LVCMOS, LVCMOS2, LVCMOS1.8, LVCMOS1.5, and LVCMOS1.2.
Input receivers 140 and 141 are NMOS type and PMOS type differential input receivers, respectively, each having one of their input coming from the input pad 180 and the other input connected to the reference voltage VREF. Their outputs 191 and 192 are also connected to one of the inputs of the multiplexer 160. The input receiver 140 is compatible with input interface standards requiring higher reference voltages, like SSTL3 and SSTL2. The other input receiver 141 is compatible with input interface standards requiring lower reference voltages, like HSTL, GTL and GTLP.
FIGS. 2(a), 3 and 4 show the internal circuitry of the input receivers 150, 140 and 141 respectively. For ease of understanding, enable circuitry from each of the receivers is removed. Detailed explanation of the prior art can be found in U.S. Pat. No. 5,958,026 titled “Input/Output Buffer Supporting Multiple I/O Standards”.
In the method employed in the existing input circuitry for FPGAs as shown in FIGS. 1–4, the first difficulty is with designing the Schmitt trigger. It is very difficult to design a Schmitt trigger that supports number of general purpose standards. This is because supporting a number of general purpose standards requires that maximum input voltage for logic low (Vilmax) and minimum input voltage for logic high (Vihmin)) of the Schmitt trigger be kept such that they satisfy Vilmax and Vihmin specifications of all the desired standards. In effect of this, maximum and minimum limits within which Schmitt trigger's trip point must remain, becomes tighter, and therefore variation in operating conditions (PVT) easily makes the trip point to move outside the limits. So a Schmitt trigger that supports one standard nicely may not be working well for other desired standards.
For an example, a Schmitt trigger shown in FIG. 2(a) is sized to support general-purpose standards, namely, 5V CMOS, LVTTL, LVCMOS, LVCMOS-2.5V, LVCMOS-1.8, LVCMOS-1.5V and LVCMOS-1.2V. The limits for its trip-point variation for a given standard are set by Vilmax and Vihmin specification of the standard. Table 1 shows the Vihmin and Vilmax specifications of the desired standards. It is to be noted that power supply VCCI of the Schmitt trigger 150 can vary with standard, which is also specified in Table 1. For details JEDEC standard of corresponding general purpose standard can be referred.
TABLE 1StandardsVilmaxVihminVCCI5 V CMOS1.03.53.3LVTTL0.82.03.3LVCMOS0.82.03.3LVCMOS-2.5 V0.71.72.5LVCMOS-1.8 V0.631.171.8LVCMOS-1.5 V0.520.971.5LVCMOS-1.2 V0.420.781.2
FIGS. 2(b) through 2(d) show the variation in trip point of a Schmitt trigger with different operating conditions for general-purpose standards. All the characteristic curves of Schmitt trigger 150 are plotted for the output 190 against the input 197. Each figure has three curves, one at a typical condition while other two are at extreme conditions, SF (Slow models for NMOS, Fast Models for PMOS, temperature and power supply are best) and FS (Fast models for NMOS, Slow models for PMOS and temperature and supply voltage are the worst).
FIG. 2(b) shows Schmitt trigger's characteristic curves for a nominal 3.3 volt VCCI supply. In this case, Schmitt trigger supports 5V CMOS, LVTTL and LVCMOS standards. Curve 3.3_typ is plotted for typical operating conditions and curves 3.3_fs and 3.3_sf are plotted for two extreme operating conditions. It can be seen that extreme curves are within the Vihmin and Vilmax limits marked in the figure. So in this case, the Schmitt trigger is operating within the specifications of 5V CMOS, LVTTL and LVCMOS standards.
FIG. 2(c) shows Schmitt trigger's characteristic curves for nominal 2.5 volt and 1.8V VCCI supplies supporting LVCMOS-2.5V, LVCMOS-1.8V standards respectively. Similar to FIG. 2(b), curves for typical and extreme operating conditions are plotted. In the case of LVCMOS-2.5V, extreme curves are within the Vihmin and Vilmax limits but for the LVCMOS-1.8V case extreme curves move outside the Vihmin and Vilmax limits. So in this case, the Schmitt trigger is operating within the specifications of LVCMOS-2.5V but violates the specifications of LVCMOS-1.8V.
FIG. 2(d) shows Schmitt trigger characteristic curves for nominal 1.5 volt and 1.2V VCCI supplies supporting LVCMOS-1.5, LVCMOS-1.2 standards respectively. Similar to FIG. 2(c), curves for typical and extreme operating conditions are plotted. Here both LVCMOS-1.5V and LVCMOS-1.2V, extreme curves move outside the Vihmin and Vilmax limits. So in this case the Schmitt trigger violates specifications of both LVCMOS-1.5V and LVCMOS-1.2V standards.
From the example, it is apparent that a Schmitt trigger designed to support a number of general-purpose standards, supports some of the standards nicely but violates specification of others. It is also to be noted that, even though performing within the specification, a large variation in trip point is not desirable, as it will be affecting the duty cycle and the quality of the signal.
Secondly, it is desirable to have a single input receiver circuitry capable of supporting most of the interfacing standards, instead of having a number of receivers in parallel and then selecting the output of the desired one.